1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more specifically to a nonvolatile semiconductor memory device capable of electrical writing/erasing and a method of manufacturing same.
2. Description of Related Art
A split gate nonvolatile memory is known as one kind of a nonvolatile semiconductor memory device capable of electrical writing/erasing (for example, see Japanese Patent Application Publication JP-A-Heisei, 9-92734, which is referred to as Patent Literature 1). In the split gate nonvolatile memory, only a part of a control gate overlaps with a floating gate. The floating gate and a part of the control gate are provided on a channel region, and thus not only the floating gate but also this part of the control gate are used for switching. Thus, the split-gate nonvolatile memory has an advantage that an excessive erasing error is prevented.
A threshold voltage of a nonvolatile memory cell transistor varies depending on an amount of charges held by the floating gate. For example, in the case of an N-channel memory cell, through a program operation, electrons are implanted into the floating gate and thus the threshold voltage increases. On the other hand, through an erasing operation, the electrons are drawn out from the floating gate and thus the threshold voltage decreases. At time of a reading operation, a read current does not flow to a program cell, but the read current flows to an erasing cell. Therefore, comparison between an amount of the read current and a predetermined reference current Iref makes it possible to sense data stored in the memory cell transistor. A transistor the same as the memory cell transistor is conventionally used as a reference transistor for generating this reference current Iref (see Japanese Patent Application Publication JP2005-72578A, which is referred to as Patent Literatures 2, and JP 2007-273593A, referred to as Patent Literature 3). This reference transistor is fixed in an erasing state.
FIG. 1 is a sectional view showing a semiconductor memory device disclosed in Patent Literature 2. Referring to FIG. 1, a semiconductor substrate 100 is divided into: a memory cell region where a flash memory cell is formed; and a logic region where a logic device is formed. The semiconductor substrate is divided into an active region and a field region 101.
On the memory cell region, a split gate electrode structure 130 is formed. In this split gate electrode structure 130, split gate oxide film patterns 102a, floating gates 104a, and silicon oxide film patterns 110 are deposited, and inside a gap between the silicon oxide film patterns 110, a source line 120 connected to the semiconductor substrate 100 is provided. At a portion of the substrate connected to the source line 120, impurity is doped to form a source region 203.
The split gate oxide film pattern 102a is provided as a floating gate oxide film pattern of a flash memory and the floating gate 104a is provided by a split gate pattern.
Along profiles of surfaces of the split gate electrode structure 130 and the semiconductor substrate 100, a silicon oxide film 132 is provided. This silicon oxide film 132 is provided as a gate oxide film of a logic device, a word line oxide film, and a tunnel gate between a split gate pattern and a word line.
On both sides of the split gate electrode structure 130 where the silicon oxide film 132 is formed, control gates 150 are provided. This control gate 150 has a shape with its lower outer side surface more projected laterally than its upper outer side surface. That is, the channel length of the control gate 150 is further extended by the length by which its lower side surface is projected laterally.
An upper tip on one side surface of the floating gate 104a opposing the control gate 150 has a sharp-pointed shape. Thus, charges filled in the floating gate 104a are easily released to the control gate 150 through this tip portion. Moreover, at time of programming, a voltage applied to the control gate 150 is easily coupled to the floating gate 104a. 
In the logic region, a logic gate pattern 152 is provided which has a thickness thinner than the channel length of the control gate 150. Providing the shape such that the lower side surface of the control gate 150 is projected laterally permits ensuring the channel length of the control gate 150 regardless of the thickness of the logic gate pattern 152.
FIGS. 2A to 2G are sectional views illustrating a method of forming a semiconductor device disclosed in Patent Literature 2. Referring to FIG. 2A, the memory region where the memory cell is formed and the logic region where the logic device is formed are sectionalized on the semiconductor substrate 100. The active region and the field region 101 are formed by applying normal element isolation processing. For this element isolation processing, a Shallow Trench Isolation (STI) processing is preferably used.
Subsequently, on the semiconductor substrate 100, the first silicon oxide film 102, a floating gate first polysilicon film 104, and a first nitride film are sequentially formed. Subsequently, a predetermined portion of the first nitride film formed on the memory cell region is etched by a normal photolithography processing to form a first nitride film pattern 106 for defining a floating gate region.
Referring to FIG. 2B, by using the first nitride film pattern 106 as a mask, the floating gate first polysilicon film 104 is partially subjected to isotropic etching. As a result of carrying out the isotropic etching step, an edge of the floating gate first polysilicon film 104 is rounded since a film etching speed of the edge portion of the floating gate first polysilicon film 104 in contact with the first nitride film pattern 106 is relatively slower. The isotropic etching includes plasma etching and wet etching.
A portion where the edge of the floating gate first polysilicon film 104 is curved serves as an upper tip portion of a split gate pattern formed through subsequent processing. Therefore, the upper tip portion of the split gate pattern formed by the subsequent processing consequently has a sharp-pointed shape.
Referring to FIG. 2C, a second silicon oxide film 108 is formed along top and side surfaces of the first nitride film pattern 106 and a top surface of the floating gate first polysilicon film 104. Referring to FIG. 2D, the second silicon oxide film 108 is subjected to anisotropic etching to form silicon oxide film patterns 110 on side surfaces of the first nitride film pattern 106. At this point, the anisotropic etching is carried out in such a manner that the floating gate first polysilicon film 104 is exposed to a surface and the entire second silicon oxide film 108 on the top surface of the first nitride film pattern 106 is removed.
Subsequently, the floating gate first polysilicon film 104 exposed by the etching processing is etched and subsequently the first silicon oxide film 102 is etched to thereby expose a surface of the semiconductor substrate 100. The floating gate first polysilicon film 104 is divided into two parts separated from each other by this processing.
Subsequently, a silicon oxide 112 having a thin thickness is formed on a side surface of the floating gate first polysilicon film 104 so that the side surface of the floating gate first polysilicon film 104 is not exposed to outside.
Referring to FIG. 2E, impurity ions are implanted under the exposed surface of the semiconductor substrate 100 to form the source region 203. Subsequently, a second polysilicon film is formed in such a manner as to fill a gap between the silicon oxide film patterns 110. The second polysilicon film is electrically connected to the source region 203. Subsequently, the second polysilicon film is flattened in such a manner that the second polysilicon film remains in a gap between second silicon oxide film patterns and the top surface of the first nitride film pattern 106 is exposed to the outside, whereby a source line 120 is formed. As the flattering process, the CMP or etch-back processing can be adopted.
Referring to FIG. 2F, the first nitride film pattern 106 is removed and the floating gate first polysilicon film 104 and the first silicon oxide film 102 provided below the first nitride film pattern 106 are sequentially removed. Therefore, on the semiconductor substrate 100, the split gate oxide film patterns 102a, the floating gate patterns 104a, and the silicon oxide film patterns 110 are deposited, and the split gate electrode structure 130 having the split gate oxide film patterns 102a is formed between the silicon oxide film patterns 110.
Of the split gate electrode structure 130, the split gate oxide film patterns 102a are provided as a floating gate oxide film of the flash memory and the floating gates 104a are provided as a floating gate of the flash memory.
This etching step proceeds without a specially provided photomask pattern. Therefore, while the floating gate first polysilicon film 104 is etched, an upper surface of the source line 120 is partially etched. Moreover, while the first silicon oxide film 102 is etched, side surface portions of the silicon oxide film patterns 110 are partially etched.
Referring to FIG. 2G, a silicon oxide film 132 is formed along profiles of a surface of the split gate electrode structure 130 and a surface of the semiconductor substrate 100. This silicon oxide film 132 is provided as a gate oxide film of a logic element, a word line oxide film, and a tunnel gate between a first polysilicon film pattern and a word line.
Subsequently, a polysilicon film 134 is formed on the silicon oxide film 132. This polysilicon film 134 is formed with a fixed thickness along the profile of the split gate electrode structure 130. Therefore, the polysilicon film 134 is formed such that a portion where the split gate electrode structure 130 is formed is projected relative to its surroundings. The polysilicon film 134 is formed to be a word line of the flash memory cell and a gate electrode of the logic device.
Here, the manufacturing processes of FIGS. 2E to 2F will be described in more detail. FIG. 2H shows the memory cell region in FIG. 2E. The first nitride film pattern 106 is removed by wet etching, so that the side surfaces of the silicon oxide film patterns 110 and the top surface of the floating gate first polysilicon film 104 are exposed (FIG. 2I). Subsequently, the floating gate first polysilicon film 104 located immediately below the removed first nitride film pattern 106 is removed by dry etching (FIG. 2J). At this point, the remained floating gate first polysilicon film 104 is formed as the floating gate 104a. Subsequently, the first silicon oxide film 102 is removed by wet etching (FIG. 2K). At this point, the side surfaces of the silicon oxide film patterns 110 are recessed by the wet etching.